Logic Investigator for Altera EQN (and eventually other formats).

Logic Investigator (li) allows a designer to explore the characteristics of a logic design. Originally, it was focused on inspecting a design with muliple clock domains and identifying every path that crosses between domains (specifically, every source flop and destination flop). However, the tool is based on the idea of parsing a design description (currently just Altera's EQN format) to build data structures representing the design, then allowing a user to perform specific checks. Several checks have been added so far, many more are possible.

What 'li' can do today includes:
- report every flop pair representing a clock domain crossing.
- report just the clock domain crossings where more than one signal
  from one domain is combined to end at a flop in another domain, and
  where a signal from one domain ends at more than one flop in another
  domain.
- report any starting point (flop or design input) that propagates to both
  set/reset and other inputs to flops (helps identify flops that were accidentally
  left out of the reset clause in the RTL).
- report all design inputs that propagate to more than one flop (finds inputs
  that won't use IO cell flops) and design outputs that propagate from more
  than one flop (outputs that won't use IO cell flops).
- for every design IO, report the associated clock domain(s).
- trace all possible paths from a starting flop to a destination flop (can report
  forwards or backwards).
- read a list of exceptions (regular expressions allowed) for all checks
- read Altera EQN format.

The Altera EQN format is the current input format, but I believe that adding XNF or EDIF will be straightforward. Parsing gate level descriptions is certainly the easiest starting point, but I would also like to develop a way to get 'li' to work with RTL code. I'd like to find some open source way to convert RTL to a generic gate description, somewhat like what you get if you use Design Compiler to read RTL then immediately write it back out (the GTECH library). The verilog parser in Icarus is probably a good starting point, although the "synthesis" ability in Icarus lags far behind the simulation ability.

Using 'li': invoke 'li' with the name of the EQN file to read. After reading the design, 'li' will present a command prompt.
  % li <eqn filename>
  li: reading design
  li> 

Commands supported today are:

excl[usionfile] <exclusion file> - read a file to get pairs of flops to exclude from reports. PERL regular expressions are supported. Names may be either the short or long EQN names.

cross[ing_report] - generate a list of all source flops that propagate to flops in other clock domains (for each source flop, lists all destinations in other domains)

dang[erous_crossings] - only report crossings with multiple sources, multiple destinations, or multiple paths.

io_r[eport] - generate a list of all flops related to every design IO signal, including clock at the flops

io_f[lop_report] - list all IO signals that connect directly to single flops such that the flops are likely to be IO flops.

io_n[otflop_report] - list all IO signals that do NOT connect directly to single flops.

res[et_check] - report any signal that propagates to both set/reset and non-set/reset pins of flops

trace_fwd <start> <end> - report all paths between the start and end points

trace_back <start> <end> - reverse trace, same as trace_fwd.


All output written to the screen is also written to li.log.