There are 3 main points to making high speed state machines by one-hot encoding:
Also, these points are also recommended:
(the designer should choose based on complexity of generated logic)
Simple example:
reg [2:0] state ;
parameter IDLE=0, RUN=1, DONE=2 ;
always @ (posedge clock or negedge resetl)
if ( ! resetl) begin
state <= 3'b001 ;
out1 <= 0 ;
end
else begin
state <= 3'b000 ;case (1'b1) // synthesis parallel_case full_case
state[IDLE]:
if (go)
state[RUN] <= 1 ;
else
state[IDLE] <= 1 ;
state[RUN]:
if (finished)
state[DONE] <= 1 ;
elsestate[RUN] <= 1 ;state[DONE]:
state[IDLE] <= 1 ;
endcase
out1 <= state[RUN] & ! finished ;
end
If you want to read
more in depth about all of these points, including why one-hot is useful
for high speed, read this longer
writeup.
I arrived at the
conclusions here on my own, but around the same time, Cliff Cummings
presented a paper at SNUG San Jose 2003 that included these same points: Cliff's
paper Cliff's website