Best Practices for One-Hot State Machine, coding in Verilog

There are 3 main points to making high speed state machines by one-hot encoding:

  1. Use 'parallel_case' and 'full_case' directives on a 'case (1'b1)' statement
  2. Use state[3] style to represent the current state
  3. Assign next state by:

Also, these points are also recommended:

(the designer should choose based on complexity of generated logic)

Simple example:

reg [2:0]  state ;

parameter  IDLE=0, RUN=1, DONE=2 ;

always @ (posedge clock or negedge resetl)

  if ( ! resetl) begin

    state <= 3'b001 ;

    out1 <= 0 ;


  else begin

state <= 3'b000 ;

case (1'b1) // synthesis parallel_case full_case


if (go)

  state[RUN] <= 1 ;


  state[IDLE] <= 1 ;


if (finished)

  state[DONE] <= 1 ;

  state[RUN] <= 1 ;


state[IDLE] <= 1 ;


out1 <= state[RUN] & ! finished ;


If you want to read more in depth about all of these points, including why one-hot is useful for high speed, read this longer writeup.

I arrived at the conclusions here on my own, but around the same time, Cliff Cummings presented a paper at SNUG San Jose 2003 that included these same points: Cliff's paper Cliff's website