`timescale 1ns / 10ps

module cbaf_cgss_tb ;
   reg           clk = 1 ;
   reg           rstl = 1 ;
   always #5 clk = ~clk ;
   initial #5  rstl = 0 ;
   initial #25 rstl = 1 ;
   initial $vcdpluson() ;

   wire          spi_clk = clk ;
   reg           spi_select = 1 ;
   reg           mosi = 0 ;
   wire          miso ;
   reg [7:0]     status1 = 8'hCB ;
   wire [7:0]    control1 ;
   reg [15:0]    k ;
   reg [7:0]     miso_shift = 0 ;

   always @ (posedge spi_clk or negedge rstl)
     if (~rstl)
       miso_shift <= 0 ;
     else
       miso_shift <= {miso_shift, miso} ;

   task sgss_write ;
      input [7:0] address ;
      input [7:0] data ;
      begin
         @ (negedge spi_clk) mosi = 0 ;
         spi_select = 0 ;
         for (k=0; k<6; k=k+1)
           @ (negedge spi_clk) ;
         @ (negedge spi_clk) mosi = 1 ;
         for (k=0; k<8; k=k+1)
           @ (negedge spi_clk) mosi = address[7-k] ;
         for (k=0; k<8; k=k+1)
           @ (negedge spi_clk) mosi = data[7-k] ;
         @ (negedge spi_clk) mosi = 0 ;
         spi_select = 1 ;
         $display ($stime, " spi write data 0x%0x at addr 0x%0x",data,address);
      end
   endtask

   task sgss_read ;
      input [7:0] address ;
      begin
         @ (negedge spi_clk) mosi = 0 ;
         spi_select = 0 ;
         for (k=0; k<7; k=k+1)
           @ (negedge spi_clk) ;
         for (k=0; k<8; k=k+1)
           @ (negedge spi_clk) mosi = address[7-k] ;
         for (k=0; k<8; k=k+1)
           @ (negedge spi_clk) mosi = 0 ;
         @ (negedge spi_clk) mosi = 0 ;
         spi_select = 1 ;
         $display ($stime, " spi read of addr 0x%0x: data 0x%0x", address,
                   miso_shift) ;
      end
   endtask

   cbaf_cgss DUT
     (/*AUTOINST*/
      // Outputs
      .miso                             (miso),
      .control1                         (control1[7:0]),
      // Inputs
      .spi_clk                          (spi_clk),
      .rstl                             (rstl),
      .spi_select                       (spi_select),
      .mosi                             (mosi),
      .status1                          (status1[7:0]));


   initial begin
      #100 ;
      sgss_write (8'hA4, 8'h34) ;
      sgss_read (0) ;
      sgss_read (1) ;
      sgss_write (0, 8'h34) ;
      sgss_read (0) ;
      sgss_read (1) ;
      #20 ;
      $finish ;
   end


endmodule