How to share a set of CSRs between 2 separate processor interfaces. This is simplest if both interfaces are operating on the same clock, but it would be possible to use one clock as the main clock, and send read and write enables across clock boundaries using synchronizers and ack signals back, also using synchronizers (address and data would not need synchronizers as long as they are held steady for the duration of the transaction). The %READCASE and %WRITECASE instantiations of the read and write muxes can be used more than once, so: %RD readbus %VCL readbus = 0 ; case (address1) %READCASE endcase readbus1 = readbus ; readbus = 0 ; case (address2) %READCASE endcase readbus2 = readbus ; %E would create two separate read busses. Two %WRITECASE statements are used similarly: %WD writedata %VCL writedata = writedata1 ; if (write_enable1) begin writedata = writedata1 ; case (address1) %WRITECASE endcase end else if (write_enable2) begin writedata = writedata2 ; case (address2) %WRITECASE endcase end %E