module example_lp (clk, reset_l 
 ,up_din
 ,up_addr
 ,up_csl
 ,up_rwl
 ,up_dout
 ,up_dout_ENL
 ,control1
 ,control2
 ,status1
 ,stickybit1
 ,stickybit2
 ,repeatingfield0
 ,repeatingfield1
 ,morerepeat
 ) ;


input clk, reset_l ;
input 		 up_din;
input 	[3:0]	 up_addr;
input 		 up_csl;
input 		 up_rwl;
input 	[5:0]	 status1;
input 		 stickybit1;
input 		 stickybit2;
output 	[7:0]	 up_dout;
output 		 up_dout_ENL;
output 	[7:0]	 control1;
output 	[11:0]	 control2;
output 		 repeatingfield0;
output 		 repeatingfield1;
output 	[1:0]	 morerepeat;
reg 	[7:0]	 up_dinQ ;
reg 	[3:0]	 up_addrQ ;
reg 		 up_cslQ ;
reg 		 up_cslQQ ;
reg 		 up_rwlQ ;
reg 	[7:0]	 up_dout, up_dout_D ;
reg 		 up_dout_ENL ;
reg 	[3:0]	 version ;
reg 	[3:0]	 deviceID ;
reg 	[7:0]	 control1, control1_D;
reg 	[11:0]	 control2, control2_D;
reg 		 stickybit1S, stickybit1S_D;
reg 		 stickybit2S, stickybit2S_D;
reg 		 repeatingfield0, repeatingfield0_D;
reg 		 repeatingfield1, repeatingfield1_D;
reg 	[1:0]	 morerepeat, morerepeat_D;


always @ (up_din
or up_addr
or up_csl
or up_rwl
or status1
or stickybit1
or stickybit2
or up_dinQ
or up_addrQ
or up_cslQ
or up_cslQQ
or up_rwlQ
or up_dout
or up_dout_ENL
or version
or deviceID
or control1
or control2
or stickybit1S
or stickybit2S
or repeatingfield0
or repeatingfield1
or morerepeat
) begin
  up_dout_D = up_dout ;
  control1_D = control1 ;
  control2_D = control2 ;
  stickybit1S_D = stickybit1S | stickybit1 ;
  stickybit2S_D = stickybit2S | stickybit2 ;
  repeatingfield0_D = repeatingfield0 ;
  repeatingfield1_D = repeatingfield1 ;
  morerepeat_D = morerepeat ;

up_dout_D = 0 ;
if (up_cslQQ & ! up_cslQ & up_rwlQ)
case (up_addrQ)
0: begin // 0x0
  up_dout_D[3:0] = version ;
  up_dout_D[7:4] = deviceID ;
end
1: begin // 0x1
  up_dout_D[7:0] = control1 ;
end
2: begin // 0x2
  up_dout_D[7:0] = control2[7:0] ;
end
3: begin // 0x3
  up_dout_D[3:0] = control2[11:8] ;
end
4: begin // 0x4
  up_dout_D[5:0] = status1 ;
end
5: begin // 0x5
  up_dout_D[7] = stickybit1S ;
  stickybit1S_D = 0 ;
  up_dout_D[6] = stickybit2S ;
end
6: begin // 0x6
  up_dout_D[7] = repeatingfield0 ;
  up_dout_D[6] = morerepeat[0] ;
end
7: begin // 0x7
  up_dout_D[7] = repeatingfield1 ;
  up_dout_D[6] = morerepeat[1] ;
end
endcase

if (up_cslQQ & ! up_cslQ & ! up_rwlQ)
case (up_addrQ)
0: begin // 0x0
end
1: begin // 0x1
  control1_D = up_dinQ[7:0] ;
end
2: begin // 0x2
  control2_D[7:0] = up_dinQ[7:0] ;
end
3: begin // 0x3
  control2_D[11:8] = up_dinQ[3:0] ;
end
4: begin // 0x4
end
5: begin // 0x5
  stickybit1S_D = up_dinQ[7] ;
  stickybit2S_D = (stickybit2S_D & ~up_dinQ[6]) | stickybit2 ;
end
6: begin // 0x6
  repeatingfield0_D = up_dinQ[7] ;
  morerepeat_D[0] = up_dinQ[6] ;
end
7: begin // 0x7
  repeatingfield1_D = up_dinQ[7] ;
  morerepeat_D[1] = up_dinQ[6] ;
end
endcase
end

always @ (posedge clk or negedge reset_l)
  if ( ! reset_l) begin
    up_dinQ <= 0 ;
    up_addrQ <= 0 ;
    up_cslQ <= 0 ;
    up_cslQQ <= 0 ;
    up_rwlQ <= 0 ;
    up_dout <= 0 ;
    up_dout_ENL <= 1 ;
    version <= 15 ;
    deviceID <= 14 ;
    control1 <= 0 ;
    control2 <= 0 ;
    stickybit1S <= 0 ;
    stickybit2S <= 0 ;
    repeatingfield0 <= 0 ;
    repeatingfield1 <= 0 ;
    morerepeat <= 0 ;
  end
  else begin
    up_dinQ <= up_din ;
    up_addrQ <= up_addr ;
    up_cslQ <= up_csl ;
    up_cslQQ <= up_cslQ ;
    up_rwlQ <= up_rwl ;
    up_dout <= up_dout_D ;
    up_dout_ENL <= (up_cslQ|up_rwlQ) ;
    version <= 0 ;
    deviceID <= 1 ;
    control1 <= control1_D ;
    control2 <= control2_D ;
    stickybit1S <= stickybit1S_D ;
    stickybit2S <= stickybit2S_D ;
    repeatingfield0 <= repeatingfield0_D ;
    repeatingfield1 <= repeatingfield1_D ;
    morerepeat <= morerepeat_D ;
  end
endmodule