Always be careful with clocks

One early ASIC I implemented was in a single-metal, single-polysilicon process (it was a 4 micron gate array, ~1984). It was a very clean synchronous design.

(Yes, there was a day when signals were routed partly in poly, with the penalty being significant resistance and RC delays. Chip designers had worried about RC delays at that time, then got a respite from RC delays for a little while with multiple layers of metal. Now we worry about RC delays again.)

When we got chips back, they only worked if the voltage was rather high - 5.5V or 6V (5V was the nominal operating voltage).  Obviously, that was pretty mysterious.  Eventually I worked out that the clock distribution was very poor, and in some places, hold times were not being met at some flops. This was surprising, as we did have pretty good RC extraction tools, and ran simulations with best/typical/worst case back annotated delays, which worked.

How did this happen?
  1. The routing of the clock was done poorly - I hadn't bothered to tell the automatic router to route the clock net first, which was supposed to be the standard practice (I can't recall whether or not I was ever told about that), and
  2. The actual poly resistance was way out of spec - much higher than the parameters our delay calculators were using.
If the poly sheet resistance had been in spec, the design almost certainly would have worked fine - that's what simulations had shown. How was it that no one knew/cared about the resistance? Other designs had plenty of margin, so were not affected. And process engineers aren't design engineers - they don't always know what parameters are and are not most significant.


  1. Clocks are vital in synchronous designs - treat them oh so carefully.
  2. The things that affect delays are not consistent - when two signal paths are compared, higher VDD may speed one path more than the other. Similarly, if one layer of dielectric is thinner, then routes in the metal layers it separates are affected much more than routes in other layers, so again, signals are affected in different ways. Remember that when you think you are perfectly balancing clock distribution by adding capacitance.
  3. There should be some checks on process parameters so that simulations are based on real numbers, not goals that were set long ago and never checked.
  4. Lore such as "route the clock nets first" should be written down and presented in a check list format so they are not forgotten or neglected.
  5. Clocks are vital in synchronous designs - treat them oh so carefully.
cbenz 17-Jun-2003