A virtual serial link between logic simulations

Enabling simulations at different locations to be linked by PCI Express, SONET, Serial RapidIO, Ethernet, etc.

I developed sit-link in the summer of 2005, and attempted to market it. Sadly, the greatest opportunity for sales was the probably 2003-2004, when PCI Express designs were first being done.  Lacking any sales, I've decided to release sit-link as open source.  I hope someone may find it helpful.  If you need assistance in using it, contact me at sitlink (at)
Also, here is a marketing brief that I prepared.
At present, sit-link consists of:
  1. A linux application utilizing sockets that links over a network
  2. A simulation model that collects serial data into batches that are sent as a network packet.
The simulation model communicates with the linux application through "named pipes".

C code for the linux application is sit_cli.c
A verilog model for a x4 serial link is sit_ver_x4_cdr.v - this version includes cdr logic that tracks bit width variations and reflects them at the far end. An earlier, simpler version without the cdr is sit_ver_x4.v

A readme is here: sitlink_readme.txt. It mentions a verilog test bench: x4_test.v

The C code should be Solaris ready. It also is Cygwin ready for use under windows, but only with applications that are compiled under Cygwin so that they can use Cygwin named pipes.  The main obstacles to porting to Windows will be: (1) changing to Windows named pipes, IF verilog/vhdl simulators allow access to those named pipes; (2) changing to Windows sockets; (3) finding a Windows structure like select that allows waiting/polling for work simultaneously from both sockets and named pipes, or splitting into 2 threads (tx and rx).

A VHDL port should not be too challenging, but one problem may be getting the serial data through the named pipes - most systems will accumulate a block of data (1K or 4K bytes) before sending it forward.  Verilog added a file flush in Verilog-2000, which I used in the model above.  VHDL does not appear to have a similar IO construct, so it may be necessary to add a pad packet after each real packet to push the data through the pipe.